Questions tagged with FPGA Development
Content language: English
Select up to 5 tags to filter
Sort by most recent
Browse through the questions and answers listed below or filter and sort to narrow down your results.
Hi,
Is it possible to upgrade the F1 nodes' Viti's version to 2023.2?
I am currently using the AMI 1.2 image.
1
answers
0
votes
48
views
asked 9 days agolg...
To check AMI and AFI approved by others using AWS cli,
I used the command "aws ec2 description-fpga-images > output",
An error occurred (UnauthorizedOperation) when calling the DescribeFpgaImages...
1
answers
0
votes
69
views
asked a month agolg...
hello,
on the F1 instances, is there a way to access the full 72 bit of the DDR4 banks from the CL?
our application would benefit from giving up ECC support, and having access to the extra bits in...
1
answers
0
votes
102
views
asked 3 months agolg...
I am following the documentation linked below. I was able to build the image successfully but when I try to complete step 7 I get an error in the console also shown below. Since the script that runs...
0
answers
0
votes
106
views
asked 3 months agolg...
I cannot pop up GUI when I use mobaxterm if I set emulation debug=gui in Amazon AMI here https://aws.amazon.com/marketplace/pp/prodview-hxbanceez6tso.
It should pop up if I set it when I do HW...
1
answers
0
votes
159
views
asked 4 months agolg...
Hi,
![Enter image description here](/media/postImages/original/IMHuUteqzyRb6Kfpz-x8mzJw)
Look at the above image. From **module A**, a gated clock is going to **module B**. We found that **module...
1
answers
0
votes
156
views
asked 4 months agolg...
Hi,
I was trying to read a memory from FPGA using DMA read and I got the following output.
a4,
e,
25,
3c,
28,
85,
dc,
5,
**a4,
e,
25,
3c,
28,
85,
dc,
5**.
8 bytes are repeated here.
The expected...
Accepted AnswerFPGA Development
4
answers
0
votes
204
views
asked 5 months agolg...
DMA restrictionslg...
Hi,
I want to write two different registers/memory parallelly using DMA. I tried using multithreading concept. But writing is not happening as expected. I mean there is a time delay. How to avoid it?...
1
answers
0
votes
152
views
asked 5 months agolg...
Hi,
I want to store 500 MB of data in DDR and it should be feed to my design as 64 bit data continuously using 40 MHz clock (Note: 40 MHz clock is generated using MMCM). How to achieve this.?
Thank...
Accepted AnswerFPGA Development
1
answers
0
votes
151
views
asked 6 months agolg...
Hi,
we are seeing performance drop when we access specific address pattern from DDR. Please find the below details.
in a single test we read same address repeatedly as mentioned below
rd_addr is...
1
answers
0
votes
218
views
asked 7 months agolg...
Hi there,
Is there a way that CL can control the XDMA inside the Shell in the AWS F1? I have a usecase where CL needs to setup a DMA transfer from internal memory to Host.
A separate question, Is...
1
answers
0
votes
165
views
asked 7 months agolg...
XRT ERROR : failed to load xclbin : input output error hello_world tutorial on AWS F1 / AMI 1.12.2lg...
I encountered an error during the official tutorial. (https://github.com/aws/aws-fpga/blob/master/Vitis/README.md)
I followed the tutorial in
AWS F1(f1.2xlarge) instance / oregon
FPGA Developer AMI...
Accepted AnswerFPGA Development
3
answers
0
votes
241
views
asked 7 months agolg...